The present invention relates generally to integrated circuits, and more particularly to a system to improve source-coupling ratio of integrated memory circuits.
An electrically erasable programmable read only memory (EEPROM) is not the fastest memory, but the data it holds is stable over a very long time. An EEPROM, or a flash EEPROM, is programmed as the charge on an isolated or floating gate is changed. The charge on the floating gate is derived from the MOS channel under certain voltage conditions. The required voltages strongly reverse bias either the source or the drain junction. Under such conditions, channel current arriving at that junction is greatly composed of high energy or “hot” current carriers, preferably electrons. Some of the hot electrons traversing a junction near a substrate surface are injected into an overlying oxide, and further to a neighboring structure, such as a floating, or isolated, poly gate. The efficiency of the charging of the floating gate by hot electron injection determines source-coupling ratio. The charge collected in that gate causes the gate to act just as if it had received a signal from any other source. So, the MOS transistor can be induced to switch itself and remain stable in the new state. By programming the MOS transistor to be in one state or the other, a memory function can be created.
A flash EEPROM cell is typically constructed in either of two arrangements. In a split gate arrangement, both the floating gate and the word line, or control gate, reside directly above the MOS channel and control channel current serially. In a stack gate arrangement, the floating gate resides directly above the MOS channel, and the control gate resides directly above the floating gate. The stack gate arrangement occupies slightly less lateral space. The split gate arrangement has a strong advantage of serial control, wherein the control gate can shut off current flow in the channel completely and independently of the floating gate charge condition.
The junction edge, with this function, is diffused well underneath the floating gate to maximize the overlap area for charge collection. However, as technology generations shrink semiconductor device geometries, the channel length becomes shorter, thereby increasing the likelihood of MOS punch through. As such, the MOS channel length must be rescaled without the imposition of the source junction, typically by retreating the source junction edge. However, by retreating the source junction edge from under the floating gate back towards the edge of the floating gate, source-coupling ratio may be reduced. When the source-coupling ratio is reduced, the ability to program the MOS transistor as though it is a memory device becomes more difficult and slower.
Therefore, desirable in the art of are additional designs that provide an improved source-coupling ratio in integrated circuit memories.